Generally, a memory control circuit (or “controller”) coordinates writing and reading data to and from a memory. The data may originate from a central processing unit (“CPU”), for example, to be written to the memory. Alternatively, data may be read from the memory and sent to the CPU. As the capacity of memories increases and CPUs become faster, there is a need for data to be stored and retrieved in memory at increasing speeds.
FIG. 1 is a block diagram of a control circuit 102 and a memory 104 connected together. In this example, four signals span between control circuit 102 and memory 104: a clock signal MCLK, a data signal PD, a command signal CMD, and a data strobe signal DQS. FIG. 2 is a timing diagram for reading data from memory 104 to control circuit 102. In this example, data signal PD and data strobe signal DQS are supplied from memory circuit 104 to control circuit 102.
In the example of FIG. 2, command signal CMD triggers a read command at the rising edge of the signal MCLK. Data strobe signal DQS oscillates on and off at some time after read command signal CMD. Control circuit 102 uses strobe signal DQS to “clock” or “latch” in data signal PD into memory 104 at the rising and falling edges of strobe signal DQS. In this example, the falling edge of data strobe signal DQS occurs in the middle of a data bit D0 to ensure proper latching. Further, the rising edge of data strobe signal DQS falls in the middle of a data bit D1 to ensure the proper latching.
Memory 102 is a Double Data Rate (DDR) memory, where the rising and falling edges of data strobe signal DQS are used to latch data. Memories that supply data strobe signals are typically DDR memories. Different DDR memories may supply different numbers of data strobe signals in a read cycle. In contrast, single data rate (SDR) memories, where only one of the rising or falling edge of the DQS signal is used to latch data, usually do not supply data strobe signals.
One of the challenges of control circuit 102 and memory 104 is to align the DQS signals for proper latching. Another challenge of control circuit 102 is to provide compatibility with different memory types, such as SDR memories or DDR memories that supply different numbers of data strobe signals.